1. Field of the Invention
This invention relates to semiconductor manufacturing and, in particular, to test structures or defect monitors for diagnosing processing imaged induced defects in a semiconductor product.
2. Description of Related Art
An ongoing concern in semiconductor technology is the maximization of manufacturing yield and one problem in the manufacturing of semiconductors is processing induced image defects which result in physical defects within the semiconductor product and product failure. Exemplary of processing induced image defects which cause circuit failure are open circuits in conductive lines and short circuits between adjacent conductive lines.
In a lithographic imaging process a semiconductor wafer is coated with a layer of resist and the resist layer is then exposed to an illuminating light by passing the light through a mask. The mask controls the amplitude of the light inpinging upon the wafer and the mask layer in one process is subsequently developed, non-exposed resist is removed, and the exposed resist produces the image of the mask on the wafer. The image is then plated to form the circuit.
Continued improvements in lithography have been able to print increasingly fine features allowing for smaller device dimensions and higher density devices. However, as features which are smaller than the wave length of the light used to transfer the pattern onto the wafer become increasingly smaller, it has become increasingly more difficult to accurately transfer the pattern onto the wafer.
To solve this problem phase-shifted masks and assist features on the mask have been used. Phase-shifted masks selectively alter the phase of the light transmitted through the mask in order to improve the resolution of the features on the wafer. Assist features, by contrast, are used to pattern isolated high aspect features by nesting these otherwise isolated features in order to take advantage of photoresist and tools which are optimized to pattern nested features.
Another proposed solution termed optical proximity correction (OPC) uses chosen lithographic process parameters (e.g., photoresist) so that the best overall result of dense and isolated features is achieved. To accommodate the processing problems, isolated features are enlarged relative to dense features so that the isolated features print the width that they were designed to be. Therefore, the resulting pattern in the photolithographic process has the isolated features and dense features being the same width as they were designed. This can be achieved by enlarging the isolated features, decreasing the dense features, or a combination of both. Unfortunately, in general, the pattern formed on the photoresist layer is optimized for neither the dense feature nor the isolated feature.
While the above techniques are useful to minimize process induced defects, the subject invention is directed to use of a defect monitor which is formed on the mask and printed on the wafer during the printing of the wafer product to provide an enhanced manufacturing process in which defects can be readily determined and the manufacturing process enhanced.
In the manufacture of semiconductor integrated circuits, it has become conventional to fabricate test structures during the manufacturing process which structures serve to yield reliability data on the regular product circuits. The principal reason for this is that the integrated circuits themselves cannot be probed because the interconnections in the device are neither accessible electrically nor can the regions be isolated from one another to provide accurate data. The typical monolithic integrated semiconductor circuit involves such a dense pattern of impurity regions and metallurgy interconnecting them that the components cannot be readily isolated for testing purposes. Thus, semiconductor designers have found it necessary to design test structures which are isolated from the production circuits and which structures can be tested.
One manufacturing approach is the fabrication of defect monitors on the same wafers on which the actual semiconductor devices are fabricated since the device monitors are therefore fabricated in exactly the same processing environment at exactly the time as the actual semiconductor devices. Thus, the processing defects induced on these defect monitors will be more accurately indicative of the processing defects induced in the actual products. In this approach, the defect monitors are typically fabricated within the kerf or discardable portion of the semiconductor wafer.
In general, the defect test structures comprise a serpentine line, and/or one or more interdigitated lines or combs with the serpentine line. Electrical continuity is checked on the serpentine metal line whereby if a current cannot flow through the serpentine metal line then the serpentine metal line is therefore broken or discontinuous.
Electrical continuity is also checked between the serpentine metal lines and/or at least one of the metal combs. If a current can flow between the serpentine metal line and/or between a metal comb then this implies there is bridging (or shorting) across the gap where there should not be any conductors.
The simplistic design of most electrical defect process monitors, however, samples only a fraction of the design space and process development and product ramp are often conducted electrically blind to two-dimensional imaging effects and imaging linearity. Thus the fast and efficient way of using electric circuit test is generally not available for a qualitative assessment of imaging performance.
A number of patents show conventional defect monitor test structures or modification of the test structures and exemplary patents include U.S. Pat. Nos. 3,983,479; 4,144,493; 4,801,869; 6,362,634; and 6,762,434. While the test structures disclosed therein are useful, there is still a need in the art for more reliable test structures which will enhance the efficiency of the semiconductor manufacturing process.
As used herein, the term “isolated feature” is used to refer to a feature that is approximately a distance away from the next closest feature on all edges, wherein the distance is equal to or greater than approximately four times the minimum width of a feature on a semiconductor wafer. The term “dense feature” is used for referring to a feature that is approximately a distance away from the next closest feature on all edges, wherein the distance is approximately equal to the minimum width of a feature on a semiconductor wafer. The term “space” is used to refer to the distance between the edges of two circuit features and the term “pitch” is used to refer to the distance between the centers of two circuit features. The term “jog” is used to refer to an interruption in the direction of a circuit line, typically in a right angle, to produce a jog (also termed step or notch).